1. Field of the Invention
This invention relates to a dynamic frequency divider having an even division ratio.
2. Description of the Prior Art
A frequency divider for electronic timepieces or the like is required to consume small current. When the frequency is high, it is preferable to use a dynamic frequency divider rather than a static frequency divider. In order to decrease the electric power to be consumed, use is made of an electric source voltage which is as low as possible. In this case, even though the high speed operation property of the frequency divider is deteriorated, the frequency dividing operation thereof must be effected in a reliable manner. Concerning the division ratio, a first stage frequency divider directly connected to an oscillator directly receives the output from the oscillator as a clock signal and a gate capacity supplied with the clock signal is operative as one portion of an oscillator circuit. As a result, the charging and discharging electric power of the gate capacity is fed back to the oscillator without consuming it, so that it is advantageous to make the division ratio of the first stage frequency divider more or less large. It is desirable to obtain a division ratio which is 1 to the radical number of 2 for the purpose of bringing the division ratio into agreement with the number of oscillations of a standard quartz oscillator.
In order to attain such object, a frequency divider for dividing the frequency of an applied alternating input signal by an odd integer greater than unity has heretofore been proposed. But, such conventional frequency divider has the disadvantage that use must be made of a quartz oscillator which can produce a special number of oscillations. Another frequency divider for dividing the frequency of an applied alternating input signal by 4 has also been proposed. But, such frequency divider has the drawback that the retardation time of a gate causes the operation to disturb, so that such frequency divider is unsuitable for a low electric source voltage.